Memory Management
10 by tosh | 0 comments on Hacker News.
Thursday, 31 March 2022
Wednesday, 30 March 2022
Tuesday, 29 March 2022
Monday, 28 March 2022
New top story on Hacker News: The jokes that have made people laugh for thousands of years
The jokes that have made people laugh for thousands of years
15 by wjSgoWPm5bWAhXB | 5 comments on Hacker News.
15 by wjSgoWPm5bWAhXB | 5 comments on Hacker News.
Sunday, 27 March 2022
Saturday, 26 March 2022
In a Fiery Speech Rallying Allies, Biden Denounces Putin and Seemingly Calls for His Ouster
By BY MICHAEL D. SHEAR, DAVID E. SANGER AND MICHAEL LEVENSON from NYT World https://ift.tt/EYtNvQG
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New top story on Hacker News: Show HN: Wachy – A UI for eBPF-based performance debugging
Show HN: Wachy – A UI for eBPF-based performance debugging
11 by vivek-jain | 0 comments on Hacker News.
eBPF is an amazing technology that allows safely running user-supplied functions at pretty much arbitrary probe points in a kernel/user space context. Much has been written about how amazing this feature is for kernel observability. But as someone who writes user space code, what I find even more amazing is the support for tracing arbitrary user space programs, with no code changes and low overhead. However, doing in-depth analysis can get complicated and time-consuming. My goal with wachy was to make this debugging significantly easier/faster to use, by displaying traces in a TUI next to the source code and allowing for interactive drilldown analysis. If you get a chance, check out the start of the demo video since (AFAIK) it's quite unique and gives a much clearer idea than I can provide with just text.
11 by vivek-jain | 0 comments on Hacker News.
eBPF is an amazing technology that allows safely running user-supplied functions at pretty much arbitrary probe points in a kernel/user space context. Much has been written about how amazing this feature is for kernel observability. But as someone who writes user space code, what I find even more amazing is the support for tracing arbitrary user space programs, with no code changes and low overhead. However, doing in-depth analysis can get complicated and time-consuming. My goal with wachy was to make this debugging significantly easier/faster to use, by displaying traces in a TUI next to the source code and allowing for interactive drilldown analysis. If you get a chance, check out the start of the demo video since (AFAIK) it's quite unique and gives a much clearer idea than I can provide with just text.
Friday, 25 March 2022
Thursday, 24 March 2022
New best story on Hacker News: Ask HN: Who operates at scale without containers?
Ask HN: Who operates at scale without containers?
578 by disintegore | 425 comments on Hacker News.
In other words, who runs operations at a scale where distributed systems are absolutely necessary, without using any sort of container runtime or container orchestration tool? If so, what does their technology stack look like? Are you aware of any good blog posts? edit : While I do appreciate all the replies, I'd like to know if there are any organizations out there who operate at web scale without relying on the specific practice of shipping software with heaps of dependencies. Whether that be in a container or in a single-use VM. Thank you in advance and sorry for the confusion.
578 by disintegore | 425 comments on Hacker News.
In other words, who runs operations at a scale where distributed systems are absolutely necessary, without using any sort of container runtime or container orchestration tool? If so, what does their technology stack look like? Are you aware of any good blog posts? edit : While I do appreciate all the replies, I'd like to know if there are any organizations out there who operate at web scale without relying on the specific practice of shipping software with heaps of dependencies. Whether that be in a container or in a single-use VM. Thank you in advance and sorry for the confusion.
Wednesday, 23 March 2022
Russia’s attacks on civilian targets have obliterated everyday life in Ukraine.
By BY KEITH COLLINS, DANIELLE IVORY, JON HUANG, CIERRA S. QUEEN, LAURYN HIGGINS, JESS RUDERMAN, KRISTINE WHITE AND BONNIE G. WONG from NYT World https://ift.tt/5KLsZ9m
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Tuesday, 22 March 2022
Monday, 21 March 2022
Sunday, 20 March 2022
Saturday, 19 March 2022
Friday, 18 March 2022
Thursday, 17 March 2022
Wednesday, 16 March 2022
Tuesday, 15 March 2022
Monday, 14 March 2022
New top story on Hacker News: Cascading failures in large-scale distributed systems
Cascading failures in large-scale distributed systems
7 by firstSpeaker | 0 comments on Hacker News.
7 by firstSpeaker | 0 comments on Hacker News.
Sunday, 13 March 2022
Saturday, 12 March 2022
Friday, 11 March 2022
New top story on Hacker News: Launch HN: Tensil (YC S19) – Open-Source ML Accelerators
Launch HN: Tensil (YC S19) – Open-Source ML Accelerators
14 by tdba | 30 comments on Hacker News.
Hello HN! I'm Tom, co-founder at Tensil ( https://www.tensil.ai/ ). We design free and open source machine learning accelerators that anyone can use. A machine learning inference accelerator is a specialized chip that can run the operations used in ML models very quickly and efficiently. It can be either an ASIC or an FPGA, with ASIC giving better performance but FPGA being more flexible. Custom accelerators offer dramatically better performance per watt than existing GPU and CPU options. Massive companies like Google and Facebook use them to make training and inference cheaper. However, everyone else has been left out: small and mid-sized companies, students and academics, hobbyists and tinkerers currently have no chance of getting ML hardware that perfectly suits their needs. We aim to change that, starting with ML inference on embedded and edge FPGA platforms. Our dream is that our accelerators help people make new applications possible that simply weren't feasible before. We believe that advances in AI go hand in hand with advances in computing hardware. As a couple of software and ML engineers hoping to live in a world alongside intelligent machines, we wanted to know why those hardware advances were taking so long! We taught ourselves digital design and gradually realized that the next generation of hardware will need to be finely customized to enable state of the art ML models at the edge, that is, running on your devices and not in the cloud. In the CPU world, the RISC-V RocketChip implementation has proven the value of customizable compute hardware. The problem was that no-one was building that kind of capability for ML acceleration. We started Tensil to build customizable ML accelerators and see what kind of applications people can create with them. Tensil is a set of tools for running ML models on custom accelerator architectures. It includes an RTL generator, a model compiler, and a set of drivers. It enables you to create a custom accelerator, compile an ML model targeted at it, and then deploy and run that compiled model. To see how to do this and get it running on an FPGA platform, check out our tutorial at https://ift.tt/xuY8GiV . We developed an accelerator generator in Chisel and then wrote a parameterizable graph compiler in Scala. (Fun fact: unlike in software, formal verification is actually a totally viable way to test digital circuits and we have made great use of this technique.) The accelerator generator takes in the desired architecture parameters and produces an instance of the accelerator which can be synthesized using standard EDA tools. The compiler implements ML models using the accelerator’s instruction set and can target any possible instance of the accelerator. Currently, the accelerator architecture is based around a systolic array, similar to well-known ML ASICs. You can view the architecture spec in our documentation. The compiler performs a wide variety of tasks but is optimized for convolutional neural networks. There are also drivers for each supported platform, currently limited to FPGAs running bare-metal or with a host OS. When you tell the driver to run your ML model, it sets up the input data and then streams the compiled model into the accelerator. The accelerator independently accesses host memory during execution. When the accelerator is done, the driver is notified and looks for the output in the pre-assigned area of host memory. How are we different from other accelerator options? There are many ML ASICs out there but they are all locked into a single architecture, whereas we have customization at the core of our technology. This offers the potential for a better trade-off between performance/price/watts/accuracy. Compared with other FPGA options, Xilinx DPU is great but it’s closed source and can be difficult to work with if your model is in any way customized. By going open source, we aim to support the widest possible range of models. FINN is a very cool project but requires big changes to your model in order to work, and also typically requires large FPGAs which are unsuitable for edge deployments. We work out of the box with any model (no need to quantize), and on small edge FPGAs. For embedded systems, tflite/tfmicro are great for deploying very small ML models on extremely constrained edge devices, but they are limited in terms of the performance and accuracy that can be achieved. Our tools allow you to work with full size state of the art models at high accuracy and speed. Currently we're focused on the edge and embedded ML inference use case. If you run ML models using any of the major frameworks (TensorFlow/Keras, PyTorch, etc.) on small, embedded or edge devices then Tensil is a good fit for you right now. If you primarily run inference in the data center or need lots of training acceleration, reach out to us and we can walk you through our roadmap. For now we are focused on CNN inference on edge FPGA platforms, but our aim is to support all model architectures on a wide variety of fabrics for both training and inference. The core technology will always be free and open source, but we plan to offer a “pro” version with extra enterprise features under a dual license arrangement, similar to Gitlab. We are also working on a cloud service for running our tools in a hosted setup, in which you’ll be able to run a search across all possible Tensil architectures to automatically find the best FPGA for your model. If you're interested to learn more, check out our docs ( https://ift.tt/aGV7W53 ), our Github repo ( https://ift.tt/a5g1bWq ) and join our Discord ( https://ift.tt/UKqHdLP ). And feel free to reach out any time (email in profile). We’re here to enable you to develop amazing new ML based applications, so we’d love to hear your experiences of working with ML compute hardware, whether it be CPU, GPU, or some other specialized platform. Have you had to make major changes to your ML models to get them to run on the available hardware? Are there any cool features or UX improvements that you wish hardware makers would add? Are there features that you’d like to add to your own applications but don’t know how you’d get them to work on an edge device? Looking forward to your comments!
14 by tdba | 30 comments on Hacker News.
Hello HN! I'm Tom, co-founder at Tensil ( https://www.tensil.ai/ ). We design free and open source machine learning accelerators that anyone can use. A machine learning inference accelerator is a specialized chip that can run the operations used in ML models very quickly and efficiently. It can be either an ASIC or an FPGA, with ASIC giving better performance but FPGA being more flexible. Custom accelerators offer dramatically better performance per watt than existing GPU and CPU options. Massive companies like Google and Facebook use them to make training and inference cheaper. However, everyone else has been left out: small and mid-sized companies, students and academics, hobbyists and tinkerers currently have no chance of getting ML hardware that perfectly suits their needs. We aim to change that, starting with ML inference on embedded and edge FPGA platforms. Our dream is that our accelerators help people make new applications possible that simply weren't feasible before. We believe that advances in AI go hand in hand with advances in computing hardware. As a couple of software and ML engineers hoping to live in a world alongside intelligent machines, we wanted to know why those hardware advances were taking so long! We taught ourselves digital design and gradually realized that the next generation of hardware will need to be finely customized to enable state of the art ML models at the edge, that is, running on your devices and not in the cloud. In the CPU world, the RISC-V RocketChip implementation has proven the value of customizable compute hardware. The problem was that no-one was building that kind of capability for ML acceleration. We started Tensil to build customizable ML accelerators and see what kind of applications people can create with them. Tensil is a set of tools for running ML models on custom accelerator architectures. It includes an RTL generator, a model compiler, and a set of drivers. It enables you to create a custom accelerator, compile an ML model targeted at it, and then deploy and run that compiled model. To see how to do this and get it running on an FPGA platform, check out our tutorial at https://ift.tt/xuY8GiV . We developed an accelerator generator in Chisel and then wrote a parameterizable graph compiler in Scala. (Fun fact: unlike in software, formal verification is actually a totally viable way to test digital circuits and we have made great use of this technique.) The accelerator generator takes in the desired architecture parameters and produces an instance of the accelerator which can be synthesized using standard EDA tools. The compiler implements ML models using the accelerator’s instruction set and can target any possible instance of the accelerator. Currently, the accelerator architecture is based around a systolic array, similar to well-known ML ASICs. You can view the architecture spec in our documentation. The compiler performs a wide variety of tasks but is optimized for convolutional neural networks. There are also drivers for each supported platform, currently limited to FPGAs running bare-metal or with a host OS. When you tell the driver to run your ML model, it sets up the input data and then streams the compiled model into the accelerator. The accelerator independently accesses host memory during execution. When the accelerator is done, the driver is notified and looks for the output in the pre-assigned area of host memory. How are we different from other accelerator options? There are many ML ASICs out there but they are all locked into a single architecture, whereas we have customization at the core of our technology. This offers the potential for a better trade-off between performance/price/watts/accuracy. Compared with other FPGA options, Xilinx DPU is great but it’s closed source and can be difficult to work with if your model is in any way customized. By going open source, we aim to support the widest possible range of models. FINN is a very cool project but requires big changes to your model in order to work, and also typically requires large FPGAs which are unsuitable for edge deployments. We work out of the box with any model (no need to quantize), and on small edge FPGAs. For embedded systems, tflite/tfmicro are great for deploying very small ML models on extremely constrained edge devices, but they are limited in terms of the performance and accuracy that can be achieved. Our tools allow you to work with full size state of the art models at high accuracy and speed. Currently we're focused on the edge and embedded ML inference use case. If you run ML models using any of the major frameworks (TensorFlow/Keras, PyTorch, etc.) on small, embedded or edge devices then Tensil is a good fit for you right now. If you primarily run inference in the data center or need lots of training acceleration, reach out to us and we can walk you through our roadmap. For now we are focused on CNN inference on edge FPGA platforms, but our aim is to support all model architectures on a wide variety of fabrics for both training and inference. The core technology will always be free and open source, but we plan to offer a “pro” version with extra enterprise features under a dual license arrangement, similar to Gitlab. We are also working on a cloud service for running our tools in a hosted setup, in which you’ll be able to run a search across all possible Tensil architectures to automatically find the best FPGA for your model. If you're interested to learn more, check out our docs ( https://ift.tt/aGV7W53 ), our Github repo ( https://ift.tt/a5g1bWq ) and join our Discord ( https://ift.tt/UKqHdLP ). And feel free to reach out any time (email in profile). We’re here to enable you to develop amazing new ML based applications, so we’d love to hear your experiences of working with ML compute hardware, whether it be CPU, GPU, or some other specialized platform. Have you had to make major changes to your ML models to get them to run on the available hardware? Are there any cool features or UX improvements that you wish hardware makers would add? Are there features that you’d like to add to your own applications but don’t know how you’d get them to work on an edge device? Looking forward to your comments!
Thursday, 10 March 2022
New top story on Hacker News: A word used only by Postgres developers
A word used only by Postgres developers
101 by ccleve | 45 comments on Hacker News.
I came across a word in the Postgres source code that I'd never seen before: "frammish". https://ift.tt/hHYFMd2... : > Therefore, they offer both exclusive and shared lock modes (to support read/write and read-only access to a shared object). There are few other frammishes. User-level locking should be done with the full lock manager --- which depends on LWLocks to protect its shared state. It sort of makes sense in context, as a "feature" or a "flourish". It also appears on the pg_hackers mailing list: > There has been some talk of separating the power to create new users from the power of being superuser (although presumably only a superuser should be allowed to create new superusers). If the planned pg_role rewrite gets submitted before the 8.1 feature freeze, I might look at adding that frammish into it. and here, from 19 years ago: > And we get ragged on regularly for the non-SQL-standard features we've inherited from Berkeley Postgres (eg, the implicit-FROM frammish that was under discussion yesterday). No amount of googling turns up a formal definition or usage outside of the Postgres community. "frammish.org" doesn't seem to be related. Are Postgres developers starting to evolve their own dialect? Should we call an anthropologist?
101 by ccleve | 45 comments on Hacker News.
I came across a word in the Postgres source code that I'd never seen before: "frammish". https://ift.tt/hHYFMd2... : > Therefore, they offer both exclusive and shared lock modes (to support read/write and read-only access to a shared object). There are few other frammishes. User-level locking should be done with the full lock manager --- which depends on LWLocks to protect its shared state. It sort of makes sense in context, as a "feature" or a "flourish". It also appears on the pg_hackers mailing list: > There has been some talk of separating the power to create new users from the power of being superuser (although presumably only a superuser should be allowed to create new superusers). If the planned pg_role rewrite gets submitted before the 8.1 feature freeze, I might look at adding that frammish into it. and here, from 19 years ago: > And we get ragged on regularly for the non-SQL-standard features we've inherited from Berkeley Postgres (eg, the implicit-FROM frammish that was under discussion yesterday). No amount of googling turns up a formal definition or usage outside of the Postgres community. "frammish.org" doesn't seem to be related. Are Postgres developers starting to evolve their own dialect? Should we call an anthropologist?
